Nishi Pandey Sharma

Assistant Professor

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About

Qualifications

BE ,M.Tech (RGPV, Bhopal)

Teaching Experience

5 years

Publications

02

Contact

pandeynishi738@gmail.com

  • Nishi Pandey, Virendra Singh, “A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier using Modified CSA”, Int. Journal of Engineering Research and Applications www.ijera.com ISSN: 2248-9622, Vol. 5, Issue 10, (Part – 1) October 2015, pp.81-85.
  • Nishi Pandey, Virendra Singh, “Comparison of Adders for optimized Exponent Addition circuit in IEEE754 Floating point multiplier using VHDL”, International Journal of Engineering Research and Development e-ISSN: 2278-067X, p-ISSN: 2278-800X, www.ijerd.com Volume 11, Issue 07 (July 2015), PP.60-65
  • “Review Error Detection and Correction” 2nd IEEE of Binary Codes for International conference on Electronics, Communication and Aerospace Technology (ICECA 2018)
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